1. Field of the Invention
The present invention relates to a method for fabricating a highly integrated semiconductor device, and more particularly to a method for fabricating contacts of a semiconductor device capable of achieving a reduction in contact resistance.
2. Description of the Prior Art
As techniques have been developed to fabricate highly integrated semiconductor devices having microstructures, parasitic resistance generated in metal wiring structures has been highlighted as an important problem. Such a parasitic resistance results mainly from an increase in contact resistance between the metal wiring and diffusion layer. In the fabrication of general metal oxide semiconductor (MOS) devices, an ohmic contact should be provided between the metal layer and semiconductor layer. For realizing such an ohmic contact, impurity ions are present in high concentration on the surface of the semiconductor layer being in contact with the metal layer so that current flow between the metal layer and the semiconductor layer can mainly be achieved by tunneling current through the potential barrier.
Where the current component present at the contact between the metal layer and the semiconductor layer is mainly based on the tunneling, its current density can be expressed as follows: EQU J.sub.t .about.exp(-8.PHI..sub.B /E.sub.OO) (1)
wherein, PA1 E.sub.OO : g.lambda./2 (N.sub.D /.epsilon..sub.S M*) PA1 .epsilon..sub.S : dielectric constant of silicon PA1 m*: effective electron mass PA1 .lambda.: decreased Flanck's constant PA1 N.sub.D : impurity concentration
In this case, a particular contact resistance can be expressed as follows: ##EQU1##
By referring to equation (2), it can be found that the particular contact resistance is exponentially varied depending on variations in doping concentration and potential barrier.
In other words, a decrease in contact resistance can be achieved by increasing the concentration of impurities activated in the surface of the semiconductor layer and using a material exhibiting a low potential barrier as the contact metal layer.
However, there is a limitation on the increase in concentration of impurities activated in the semiconductor surface. Using a material exhibiting a low potential barrier as the contact metal layer, there is a limitation that one metal is used for both metal layers respectively being in contact with a N.sup.+ diffusion layer and a P.sup.+ diffusion layer. This is because potential barriers defined by the metal layers respectively being in contact with the N.sup.+ diffusion layer and the P.sup.+ diffusion layer are different. In a case of PtSi, it defines a low potential barrier of 0.26 together with the P.sup.+ diffusion layer and a high potential barrier of 0.84 together with the N.sup.+ diffusion layer.